Seeing Chip Testability Through a Systems Person's Eyes

System-on-Chip Testability Using LSSD Scan Structures

0740-7475/01/$10.00 © 2001 IEEE May–June 2001 Testing densely packaged very large-scale integration (VLSI) circuits has become challenging. Embedded memories and reusable cores have become common because they reduce the design time to market for complex systems. Scan design is the most commonly practiced approach to enhancing design testability. This approach lets design storage elements be con...

Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability

testability standard in the industry. Although its mandatory provisions focus narrowly on boardlevel assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard...

System Level Testability Issues of Core Based System-on-a-Chip

Testability issues of a core based system-on-a-chip (SOC) are identified and the various solutions available at the different stages of SOC evolution are discussed. It was found that a strategy at core level and system level is needed to achieve first time success of the core based SOC. The issues considered include area, power and delay overheads, Fault coverage, At speed test, Core transparen...

Author Manuscript, Published in "system-on-chip Test Architectures: Nanometer Design for Testability, System-on-chip Test Architectures: Nanometer Design for Testability 7-0

Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs

Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs